A20 Pro: the first 2nm phone chip and a unified FP8 path for LLMs on the iPhone
Apple held its September 9 event, the first keynote led by John Ternus, who took over as CEO on September 1 with Tim Cook moving to executive chairman. The product headlines were the iPhone 18 Pro and the foldable iPhone Ultra from $1,999. The engineering headline was A20 Pro: the first production 2nm chip in a phone, built on TSMC N2 with gate-all-around nanosheet transistors and WMCM packaging. Apple's slide will tell you it is faster. The detail that changes what I would build is that the Neural Engine and the GPU now share a native FP8 path.
What Apple announced
- Process: TSMC N2, 2nm GAA nanosheet. N2's trade-off is roughly +10 to 15% performance at the same power, or 25 to 30% less power at the same performance; the designer chooses.
- Packaging: WMCM integrates CPU, GPU, Neural Engine, and RAM on the wafer without an interposer, which changes thermal and bandwidth behaviour, not just clock.
- CPU: 6 cores with two desktop-class super cores, roughly +20%.
- GPU: 7 cores, +40% graphics.
- Neural Engine: 32 cores, 2x compute, native FP8.
- Memory bandwidth: +50%.
- Dates: preorders September 12, on sale September 18.
Why unified FP8 is the point
Until now, running a language model on an iPhone meant choosing an engine and living with its number format. The Neural Engine was efficient but picky about what it would run; the GPU was flexible but hungrier. With FP8 native on both, a model quantized once to FP8 can run its attention on one unit and its projections on the other without converting formats at the boundary, and a runtime can move work between them based on power state rather than dtype. That is the on-device analogue of what I described for the Mac in Apple Neural Engine for LLMs: the win is not peak TOPS, it is not paying a conversion tax every layer.
FP8 also halves the bytes per weight against FP16. Combined with 50% more bandwidth, decode throughput for a small model roughly doubles on paper before you touch a kernel. For a 3B parameter model that is the difference between a typing-speed assistant and a usable one.
A 2nm node buys you power. A unified FP8 path buys you a model that runs on the whole chip instead of a corner of it, and the second one is what you will notice.
Capacity is the wall, not throughput
Here is the constraint the keynote did not dwell on. Bandwidth and compute went up; the memory pool in a phone did not become a Mac. An FP8 7B model is about 7 GB of weights before the KV cache, and the KV cache grows with every token of context. On a device where the OS, the camera pipeline, and the foreground app all want the same RAM, the question is not how fast the model runs but whether it fits at all with a useful context length. KV cache quantization is the lever that matters more here than on a Mac, and the sizing discipline from unified memory on Macs applies with the numbers divided by ten.
What to measure when units ship
- Sustained versus peak. Run a 10-minute decode loop and watch tokens per second over time. Throttling is the real spec of a phone chip.
- Bandwidth at FP8. Measure decode throughput for a small model at FP8 against FP16 on the same device; the ratio tells you how much of the 50% you actually get.
- NE versus GPU split. Time the same model pinned to each unit and then mixed; the mixed number is the one that validates the unified path.
- Energy per token, since 25 to 30% less power at equal performance is the N2 promise most relevant to a battery.
- Resident memory at a 4K, 8K, and 16K context to find where the device starts evicting your app.
The honest gap
Every percentage here is from Apple's keynote and coverage of it: relative to a previous generation Apple chose, on workloads Apple chose. There are no independent benchmarks until devices arrive on September 18, no published RAM figure in the material I worked from, and no third-party runtime results for the FP8 path. The direction is clear; the numbers are marketing until measured.